• Their chip design targets about half the chip area and 60% less power than Arm’s Cortex-A78.
• Designed in Europe, where more than €52B has already been mobilised to build its own chips.
• Team from Arm, AMD and EPFL, advised by former leaders of Tenstorrent, AMD, Codasip and Semidynamics.
• A Romanian Venture Capital and the Bulgarian Angels Club have already invested €190,000 in this round.

Team

FIORA5 was born from a problem the team saw first-hand: while leading chip-design work for clients, Alin kept meeting chipmakers forced to combine two processor designs that didn’t fit. Darian and Alin have known each other since high school. The team brings experience from Arm, AMD, EPFL and Capgemini Engineering, and all team members will be full-time once the round closes.

Problem

Chipmakers pay millions to license processor designs that are rigid and can rarely do every job a device needs. So many license two designs and stitch them together.

Solution

FIORA5 is designed to combine fast thinking for heavy workloads and instant reaction for real-time tasks, like a robot keeping its balance, in one processor built on the open RISC-V standard. One license is meant to replace several, and a smaller, more efficient chip matters for battery-powered devices.

Opportunity

Europe needs to act on its plan to reach 20% of the global chip production. In parallel chip users face difficulties in sourcing small and energy efficient chips. 

FIORA5 aims to become Europe’s go-to designer of processors for smart devices, with its first commercial licenses by 2029.

Market

The market for RISC-V processor designs is expected to reach about $5B by 2030 (company estimate). FIORA5 expects a license fee of about €5M per design, plus a small royalty on every chip sold.

Traction

FIORA5 has signed its first co-design partner, has been selected into Silicon Catalyst’s ChipStart EU and is a member of NVIDIA Inception. €190,000 committed  in this round by a Romanian Venture Capital and the Bulgarian Angel Club.

Use of Funds

This round funds a working prototype with measured performance, a full chip-system demo with a design partner, first partner agreements and a first patent. Together, these prepare FIORA5 for a Seed round of around €10M in 2027.

Exit

In an early acquisition scenario, a large chip company buys FIORA5 around 2028, after a working FPGA prototype but before any physical chip exists, for its team and architecture, at an estimated €15–25M. In the base case, a strategic buyer acquires the company in 2029–30, once the design is proven and backed by customer letters of intent, at an estimated €60–150M. In the upside case, FIORA5 is acquired after a Series A round, from 2031 onwards, once it has proven silicon and around 3 licenses a year, at an estimated €150M+. If FIORA5 fails to secure funding or is overtaken by competitors, the company could fail and investors could lose their entire investment.

These are company estimates and depend on FIORA5 reaching its milestones.

Risk Registry

The round that is being raised is required to build the initial prototype. To achieve commercial viability, FIORA5 will require a further equity round. This is a high risk pre-seed investment.